Fei’s Website Everything about Fei

May 1, 2009

Resume

Filed under: — Fei @ 7:49 pm

Fei Sun

 

 


 


 

Highlight of skills

  • Expertise in compiler optimization, high level synthesis, extensible processor design on Xtensa platform, custom instruction synthesis, co-processor synthesis, multiprocessor synthesis, and computer architecture analysis.
  • Extensive experience in EDA methodologies, ASIP design, ASIC design, system-on-chip design, hardware/software co-design, video codec, and RTL simulation.
  • Broad knowledge in DSP design, low power design, operating systems, computer networks, and testing for digital systems.

 


 

Work Experience

Cadence Design Systems Inc., Architect        June 2014 ~ now
Cadence Design Systems Inc., Sr. Principal Engineer        April 2013 ~ June 2014

Tensilica Inc is acquired by Cadence. Lead developer of TIE compiler.

Tensilica Inc., Principal Engineer        Feb 2013 ~ April 2013
Tensilica Inc., Staff Engineer        July 2005 ~ Feb 2013

Key member responsible for implementing and enhancing Tensilica Instruction Extension (TIE) compiler. TIE compiler (TC) is the key technology of Tensilica Inc. The compiler synthesizes custom instructions of ASIPs from high level TIE language into register transfer level (RTL) verilog. In the mean time, the custom instruction libraries for software tools (compiler, assembler, linker, simulator, etc.), scripts for hardware synthesis and verification are automatically generated.

  •          Proficient in both hardware and software parts of processor design.
  •          Expertise in instruction set architecture (ISA) and micro-architecture, and high level synthesis methodologies.
  •          Familiar with electronic design automation (EDA) methodologies.

Worked on the following projects:

  • Available upon request.

Tensilica Inc., Software Engineer (intern)        June 2004 ~ Aug. 2004

  • Optimize EEMBCTM networking benchmarks version 2 on Xtensa LX processor, achieved over 30X speedup for some benchmarks

 


 

Education

Princeton University, Princeton, NJ, Ph.D. in Computer Engineering        Nov. 2005

  • Thesis topic: Synthesis Methodologies for Embedded Extensible Processor Systems.
  • Coursework includes: computer architecture, electronic design automation, compiling techniques, low power IC and system design, operating systems, artificial intelligence, computer networks, testing for digital systems etc.

Princeton University, Princeton, NJ, M.A. in Computer Engineering        Nov. 2002

Peking University, Beijing, China, B.S. in Computer Science June 2000

  • Thesis: Novel structure sub-0.1µm SOI analysis and bulk trap/back interface states of SOI analysis

 


Research Experience

Princeton University, Assistant in Research        Sept. 2000 ~ June 2005

  • Synthesize custom processors and co-processors on extensible platforms
  • Generate and select custom instructions automatically for heterogeneous application-specific multi-processors
  • Synthesize extensible processors for scalable programs
  • Generate custom instructions automatically for application-specific instruction-set processors

Princeton University, Assistant in Teaching

  • Lab instructor for undergraduate course: system design and analysis Spring, 2004
  • Lab instructor for undergraduate course: system design and analysis Spring, 2002

NEC Laboratories America, Visitor        July 2001 ~ June 2005

  • EDA methodologies for configurable and extensible processors

 


Skills

  • Programming language skills include C/C++/Java/ML/Perl/Verilog/Vera
  • Proficient in Xtensa processor, Synopsys Design Compiler, RTL Compiler, ICC, VCS, NC, Modelsim HDL simulator, PowerTheater RTL power simulator, Prime Time, Real View, SUIF compiler, Aristotle analysis system, MPEG codec, Cyber.

 


 

Publications

Journal papers

  • F. Sun, S. Ravi, A. Raghunathan, and N. K. Jha, “A synthesis methodology for hybrid custom instruction and co-processor generation for extensible processors,” IEEE Trans. Computer-Aided Design, Nov, 2007.
  • F. Sun, S. Ravi, A. Raghunathan, and N. K. Jha, “A scalable synthesis methodology for application-specific processors,”IEEE Trans. VLSI Systems, vol. 14, no. 11, pp. 1175-1188, Nov. 2006.
  • F. Sun, S. Ravi, A. Raghunathan, and N. K. Jha, “Application-specific Heterogeneous Multiprocessor Synthesis using Extensible Processors,” IEEE Trans. Computer-Aided Design, vol. 25, no. 9, pp. 1589-1602, Sept. 2006.
  • F. Sun, S. Ravi, A. Raghunathan, and N. K. Jha, “Custom instruction synthesis for extensible processor platforms,” IEEE Trans. Computer-Aided Design, vol. 23, no. 2, pp. 216- 228, Feb. 2004.
  • F. Sun, R. Huang, J. He, A. Huang, X. Zhang, and Y. Wang, “Optimization of a sub 0.1-µm asymmetric halo SOI-MOSFET for high performance digital applications,” Chinese Journal of Electronics, vol. 10, No. 2, Apr. 2001, pp. 230-233.

Conference papers

  • F. Sun, “Automatic generation of functional models for embedded processor extensions,” in Proc. Design Automation & Test Europe (DATE) Conf., Mar. 2012, pp. 304-307.
  • F. Sun, S. Ravi, A. Raghunathan, and N. K. Jha, “Hybrid custom instruction and co-processor synthesis methodology for extensible processors,” in Proc. Int. Conf. VLSI Design, Jan. 2006.
  • F. Sun, S. Ravi, A. Raghunathan, and N. K. Jha, “Synthesis of application-specific heterogeneous multiprocessor architectures using extensible processors,” in Proc. Int. Conf. VLSI Design, Jan. 2005. pp. 551-556.
  • F. Sun, S. Ravi, A. Raghunathan, and N. K. Jha, “A scalable application-specific processor synthesis methodology,” in Proc. Int. Conf. on Computer-Aided Design, Nov. 2003, pp. 283-290.
  • F. Sun, S. Ravi, A. Raghunathan, and N. K. Jha, “Synthesis of custom processors based on extensible platforms,” in Proc. Int. Conf. on Computer-Aided Design, Nov. 2002, pp. 641-648.

Book chapters

  • F. Sun, S. Ravi, A. Raghunathan, and N. K. Jha, “A framework for extensible processor based MPSOC design”, in Embedded Processor Design – Low Power Perspective, Springer, 2007.

 


 

Reviews

  • 2016
    • CASES Technical Program Committee
  • 2015
    • CASES Technical Program Committee
  • 2014
    • CASES Technical Program Committee
  • 2013
    • IEEE Trans. Very Large Scale Integration Systems
    • CASES Technical Program Committee
  • 2012
    • ACM Trans. Embedded Computing Systems
  • 2011
    • IEEE Trans. Very Large Scale Integration Systems
    • ACM Trans. Design Automation Electronic Systems
  • 2010
    • ACM Trans. Design Automation Electronic Systems
  • 2009
    • IEEE Trans. Computer-Aided Design
    • IEEE Trans. Very Large Scale Integration Systems
    • ACM Trans. Design Automation Electronic Systems
  • 2008
    • ACM Trans. Reconfigurable Technology and Systems
    • Int. Conf. on Computer-Aided Design
    • Asia South Pacific Design Automation Conf.
  • 2007
    • Trans. Embedded Computing Systems
  • 2006
    • IEEE Trans. Computer-Aided Design
    • Int. Conf. on Computer-Aided Design
  • 2005
    • ACM Trans. Design Automation Electronic Systems
    • Int. Conf. on High Performance Computing and Communications
  • 2004
    • IEEE Trans. Computer-Aided Design
    • ACM Trans. Design Automation Electronic Systems
  • 2003
    • IEEE Trans. Computer-Aided Design

 


Talks

  • “Processor design via architecture description language specification”, guest lecture at ECE 695R, Purdue University. Prof. Anand Raghunathan, 2011

 

Activities

  • 2008
    • Treasurer of Applied Materials Toast Master Club
  • 2007
    • Member of Applied Materials Toast Master
  • 2003 – 2004
    • Committee on Honorary Degrees
    • Governance Committee of Council of the Princeton University Community (CPUC)
    • Treasurer of Council for International Graduate Students (CIGS)
    • Electrical Engineering Department representative in Graduate Student Government (GSG)
    • Conference coordinator of Third Emerging Information Technology Conference (EITC)
    • Graduate liaison of Consortium of International Student Organizations (CISO)
  • 2002 – 2003
    • President of Association of Chinese Students and Scholars at Princeton University (ACSS)
    • Conference manager of Second Emerging Information Technology Conference (EITC)
    • ACSS delegate in Graduate Student Government (GSG)
    • Deputy vice president of Association of Chinese Students and Scholars of New York (ACSSNY)
    • Drafter of ACSS Constitution

 


 

References

  • Available upon request

No Comments

No comments yet.

RSS feed for comments on this post.

Sorry, the comment form is closed at this time.

Powered by WordPress